1. Field
Example embodiments relate to a semiconductor package, a semiconductor package module including the semiconductor package, and methods of fabricating the same. More particularly, example embodiments relate to a semiconductor package including leads that can be classified into a plurality of groups and in which a plurality of semiconductor chips are stacked, and a semiconductor package module in which the semiconductor package is mounted.
2. Description of the Related Art
Semiconductor package technology is continuously being developed in order to increase the integration and operating speed of semiconductor packages, and also to reduce the size and thickness of the semiconductor packages. Semiconductor packages may be formed such that one or more semiconductor chips are attached to a lead frame. Pads may be formed on the semiconductor chips and leads may be wire-bonded and sealed with an encapsulant, e.g., as epoxy molding compound (EMC). A flash memory, for example, may use a thin small outline package (TSOP) type semiconductor package, which has a relatively small thickness. A flash memory may also have a multi chip package (MCP) type semiconductor package, in which two or more semiconductor chips may be stacked when large capacity may not be provided using a single semiconductor chip. However, in a semiconductor package in which a plurality of semiconductor chips are stacked, the whole semiconductor package may be judged as being defective if any of the semiconductor chips are defective. The pin arrangement of leads is common to all the chips, and thus non-defective semiconductor chips and defective semiconductor chips are connected together to common leads corresponding to predetermined pin numbers.
FIG. 1 is a side cross-sectional view of a prior art semiconductor package including only one chip group and one pin group. FIG. 2 is a plan view of an inner structure of the semiconductor package of FIG. 1. FIG. 3 is a plan view of the pin arrangement of the semiconductor package of FIG. 1 in the case of a NAND flash memory.
Referring to FIGS. 1, 2, and 3, a plurality of semiconductor chips 20 may be stacked on a lead frame 40. Pads 60 may be formed adjacent to two side edges of each of the semiconductor chips 20 and leads 50 may be bonded using wires 30 to the pads 60. The semiconductor chips 20 may be sealed with an encapsulant 10, e.g., epoxy molding compound (EMC). The lead frame 40 and leads 50 may be a single body.
The semiconductor package illustrated in FIGS. 1, 2, and 3 may be a NAND flash memory, in the form of a thin small outline package (TSOP) type package, or a multi chip package (MCP) type package having 48 pins. The semiconductor package may include 48 leads 50, and the pin arrangement of the leads 50 is as illustrated in FIG. 3. Hereinafter, ‘leads’ and ‘pins’ refer to an identical term in respect of the structure and function thereof. #1, #2, etc. denote the pin number of the leads. The functions of the pins are denoted next to the pin numbers, meaning the type of power or signal that is transmitted through corresponding pins, and I/O, NC, R/B, CE, Vcc, Vss, Wp, and so on are illustrated. A NAND flash memory, as illustrated in FIGS. 1, 2, and 3, may be operated using eight I/O pins and five control clocks. Examples of pins denoting five control clocks include CLE, ALE, CE (CE1 and CE2), WE, and RE.
For example, pin #29 is an I/O 0 pin, and is connected to all four semiconductor chips 20. The I/O 0 pin displays a program/erase status in a NAND flash memory. Even if just one semiconductor chip 20 positioned right above the lead frame 40 among the four semiconductor chips 20 of FIG. 1 is defective, the whole semiconductor package may malfunction. Because all the semiconductor chips 20 in the semiconductor package are connected to one I/O 0 pin, the defective semiconductor chip 20 may not be separated from the I/O 0 pin that is common to all the semiconductor chips 20.